1. Field of the Invention
This invention relates to an output circuit used in an output stage of an emitter coupled logic circuit (ECL) such as a prescaler for dividing a frequency.
2. Description of the Related Art
The circuit shown in FIG. 5 is a known output circuit used in an ECL circuit such as a prescaler, and includes a differential amplifier circuit constituted by NPN transistors Q1 and Q2, resistors R1 and R2, a constant current source I1, and a current mirror circuit constituted by NPN transistors Q4 and Q5. The above circuit is designed to increase an output current to output terminal T3 by applying a potential at node A, or at one of output nodes of the differential amplifier circuit, to the base of pull-up NPN transistor Q3, and to properly absorb a current introduced, via output terminal T3, by means of the current mirror circuit. The amount of a current introduced via output terminal T3 is equal to that of collector current Ic of transistor Q5, and can be set larger than the current supplied from constant current source I2 and used as an input current to the current mirror circuit, by making the dimensions of transistor Q5 larger than those of transistor Q4, as shown in FIG. 5.
In general, a circuit connected to output terminal T3 has an input capacitance of several pF to several tens pF. Therefore, when the frequency of an input signal supplied to input terminals T1 and T2 is high, the capacitive load of the output circuit becomes heavy. In FIG. 5, the load capacitor is indicated by CL.
At the time of the rising of an output signal which charges load capacitor CL, NPN transistor Q3 is operated as an emitter follower, so that the rate of rise of the output signal can be made high. However, at the time of discharging load capacitor CL or at the time of the falling of the output signal, current introduced or absorbed via output terminal T3 is limited by collector current Ic which is determined by current from constant current source I2, and therefore the rate of fall of the output current becomes low.
Variation of output signals Vout1 and Vout2 with respect to an input signal is shown in FIG. 6. In FIG. 6, the ordinate indicates a voltage and the abscissa indicates time. As can be seen from FIG. 6, the rate of fall of the output signal is relatively low and, therefore, transistor Q3 may be turned on before load capacitor CL is sufficiently discharged when the frequency of the input signal is high. In this case, the amplitude of the output signal is reduced, as is shown by output waveform Vout2.
The rate of fall of the output signal becomes lower as collector current Ic of transistor Q5 becomes small. Thus, the frequency response characteristics of output amplitude are deteriorated more as current Ic becomes smaller, as shown in FIG. 7. When current supplied via constant current source I2 is increased to improve its frequency response characteristic, a large amount of current must flow from power source terminal Vcc to the ground terminal, resulting in increasing the power consumption.
Since p-n junction capacitor Cbc is situated between the base and collector of transistor Q5 constituting the current mirror circuit, a displacement current flows into capacitor Cbc when an output signal voltage is changed, and it is additionally supplied as an input current to the current mirror circuit. Therefore, at the time of the rising of the output signal, a base current of transistor Q5 increases, as consequently does current Ic. Further, at the time of the falling of the output signal, the base current decreases, as does also current Ic. Such increasing/decreasing of current Ic has the effect of cancelling any change in an output current, as a result degrading the frequency response characteristics of the output amplitude.